Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
D FLIP-FLOP
PDF) Low-power high-speed performance of current-mode logic D flip-flop topology using negative-differential-resistance devices
Figure 1 from A 45 mW RTD/HBT MOBILE D-Flip Flop IC Operating up to 32 Gb/s | Semantic Scholar
Part 01: Proposal and Overview. Dual Modulus Prescaler Using Current Mode Logic Goals 2.5 GHz Operation 8/9 Dual Modulus 0.18uM BSIM 3 Model. - ppt download
PPT - Advantages of Using CMOS PowerPoint Presentation, free download - ID:3409185
Figure 5.21 from Cmos Logic and Current Mode Logic 5.1 Introduction | Semantic Scholar
Electronics | Free Full-Text | A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS
An improved current mode logic latch for high‐speed applications - Kumawat - 2020 - International Journal of Communication Systems - Wiley Online Library
PDF) Novel Differential-Mode RTD/HBT MOBILE-based D-Flip Flop IC
MC74VHC74 datasheet - Dual D Flip-Flop with Set and Reset. The MC74VHC74
Design of Low Voltage D-Flip Flop Using MOS Current Mode Logic (MCML) For High Frequency Applications with EDA Tool
An active inductor employed CML latch for high speed integrated circuits | SpringerLink
PDF) Low-power high-speed performance of current-mode logic D flip-flop topology using negative-differential-resistance devices
PDF) Resonant Tunneling Diode/HBT D-Flip Flop ICs Using Current Mode Logic-Type Monostable-Bistable Transition Logic Element with Complementary Outputs | Taeho Kim - Academia.edu
Electronics | Free Full-Text | A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS
Design of Low Power and High-Speed Cmos D Flipflop using Supply Voltage Level (SVL) Methods
Analysis and Design of High-Speed CMOS Frequency Dividers
Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
OAK 국가리포지터리 - OA 학술지 - Transactions on Electrical and Electronic Materials - High-speed CMOS Frequency Divider with Inductive Peaking Technique
Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
Energy Efficient High-Speed Links Electrical and Optical Interconnect Architectures to Enable Tera-Scale Computing
adding reset function to D Flip FLOP | Forum for Electronics
